The IEEE 1149.1 standard allows subordination of the Test Access Port (TAP) through additional pins called compliance-enable pins. This portion of the standard allows alternate IC test methods such as Level Sensitive Scan Design (LSSD) or muxed-scan IC test strategies to be used where the TAP operation may be temporarily switched off. The compliance-enable pins add one or more pins to the package that cannot be used for any other function. Compliance-enable pins can cause difficult to diagnose scan-path failures during board test when the TAP is thought to be operational but the compliance-enable pins are open or stuck-at due to a solder defect.
Compliance-enable pins have also been used by IC vendors to select a “main” TAP for the IC and “hide” the other TAPs when multiple TAP'd cores exist in the design. This presents a shorter scan path for emulation or hides details that an IC vendor may not want to provide. It also enables an IC with multiple TAPs to be IEEE 1149.1 compliant since the standard makes provision for only one TAP to be electrically visible in a single IC package. Daisy-chained IEEE 1149.1 TAPs in a System-on-Chip (SoC) requires extra test clocks to shift through the cores which can affect test and emulation performance Test data volume over IEEE 1149.1/JTAG continues to escalate especially for programming in-package FLASH in a 3D package. IEEE P1687 describes TAP operated on-chip instrumentation further increasing test data volume over the single full-duplex serial connection of IEEE 1149.1. Therefore, reducing the number of registers and Test Clocks (TCK) required can improve performance.
Methods have previously been described to deal with the limitations of the IEEE 1149.1 one bit BYPASS register and 32 bit DEVICE_ID register. The problem at the time was that Multi-Chip Modules (MCM) contain TAP'd die and a Boundary-Scan Description Language (BSDL) file for each device, but at the Printed Circuit Board (PCB) level the MCM must also present itself as a single IEEE 1149.1 compliant device with a single BSDL. The IEEE 1149.1 working group was presented with arguments for allowing these registers to be variable length, with the length defined by BSDL. This flexibility, which is allowed in any other IEEE 1149.1 register, was voted on but enough IEEE 1149.1 working group members at the time voted it down. Work has been done since then for Single Inline Packages (SiP). The approach uses an extra “STDI” input on each die and connecting all of the STDI together to the main package Test Data Input (TDI). This makes the SiP appear to have one TAP. However, this approach does not help much to shorten the scan-chain for multi-core devices. The number of loads on TDI and STDI may also limit performance. Another method has been described which requires a chip level TAP. This requires one core or die to be designed specifically for a multi-TAP package. Like previous approaches, it does not help with TAP management and reducing TCK cycles for each IR and Bypass register and it cannot be used to remove compliance-enable pins.
A TAP linking approach has also been previously described. The TAP linking approach can reduce the scan-chain TCK count in a coarse manner for each chain that is linked. It is limited as it requires a chip level or SiP package level die that has the TAP linker in it. It is a TAP itself so it cannot help with compliance-enable pins. It also introduces additional register data bits in the scan path which tools must account for. Most FPGA and CPU emulation tool software do not support these types of linking devices due to the complexity and lack of standardization of how they operate. The linker does not help remove compliance-enable pins. An “Addressable Shadow Protocol” has also been described which transmits data using TDI and TCK in the Run-Test/Idle (RTI) state. This does not work well for daisy-chains of cores with TAPs since TDI is not distributed to all of the targets, and it is not useful in removing compliance-enable pins. In addition, a method of using “fixed length” instruction registers to support multiple cores with TAPs has been described. This approach requires adding extra logic to keep the instruction width constant for the different TAPs. This appears to require significant software support and does not help with reducing compliance-enable pins.
IEEE 1149.7 describes something referred to as Zero Bit Scans. TAP0 through TAP7 modes are controlled by sequencing through the IEEE 1149.1 states of SELECT-DR, CAPTURE-DR, EXIT1-DR and then UPDATE-DR for each mode then entering the SHIFT-DR state to both lock the mode and to shift commands and data. Traversing from CAPTURE-DR to UPDATE-DR without going through SHIFT-DR is potentially hazardous as capture data then becomes update data. Because of this, IEEE 1149.7 requires that either the IDCODE or BYPASS be the loaded instructions prior to these sequences. The IEEE 1149.7 approach therefore has limitations as to what instruction is present and requires at least the TDI signal as well to shift in the command or data. IEEE 1149.7 requires direct access to the upper bits of the DEVICE_ID of an IEEE 1149.1 TAP in order to form a TAP address from those bits. This makes it difficult to use pre-built hard cores with 1149.7. It also becomes a problem in using multiple pre-designed 1149.1 compliant die in a 3D IC stack as there is no way to have addressable die via the star topology described by IEEE 1149.7. The IEEE 1149.7 also does not support enabling of compliance-enable of a TAP without a pin.